1. Field of the Invention
The present invention relates to a semiconductor device including a semiconductor, such as a transistor or a diode.
2. Description of the Related Art
A silicon insulated gate field effect transistor (hereinafter referred to as a transistor), which has been widely used for an integrated circuit or the like, has come to have some prominent problems along with the miniaturization of the circuit. The most problematic subject is the short-channel effect. The short-channel effect is phenomena that the threshold value shifts to the negative direction (the threshold value decreases) for an n-channel type transistor, and that the subthreshold characteristic is degraded (the subthreshold value increases).
The insulation of the transistor in an OFF state is maintained by formation of pn junctions between a source and a channel region and between the channel region and a drain. When the channel length becomes substantially the same as or less than the thickness of the pn junction (or the thickness of a depletion layer formed within the pn junction), the insulation due to the pn junctions is no longer sufficient; therefore, the problems as above occur.
When the channel length is set to be, for example, 1/k, it is necessary that the concentration of impurities, such as donors or acceptors, in the channel region be set k times and the thickness of a gate insulator be set 1/k in order to suppress the short-channel effect.
However, when the impurity concentration is increased or the gate insulator is thinned as above, other problems occur. First, an increase in impurity concentration causes the carrier mobility to decrease, which results in a problem in current drive capability. For example, when the channel region has an impurity concentration of 1×1015 cm−3, the electron mobility is 1400 cm2/Vs or more; however, when the channel region has an impurity concentration of 1×1019 cm−3 or more, the electron mobility is decreased down to approximately 100 cm2/Vs.
Further, when the channel region becomes miniaturized, a variation in threshold value due to the statistical fluctuation of impurities contained in the channel region (see Non-Patent Document 1) becomes unignorable. It is known that the variation in threshold value is proportional to the square root of (the impurity concentration×the thickness of the depletion layer/the area of the channel region), and the variation in threshold value will drastically increase due to an increase in impurity concentration and a decrease in channel area resulting from the channel shortening.
Since the variation in threshold value is inversely proportional to the dielectric constant of the gate insulator and is proportional to the physical thickness thereof, the variation can be suppressed by the use of a thin gate insulator having high dielectric constant; however, there is limitation on the use of a high-dielectric-constant material and on the thinning of the gate insulator.
For example, thinning the gate insulator leads to an increase in leakage current between the gate and the channel region. In particular, in a case of using silicon oxide for the gate insulator, when the thickness is 2 nm or less, the leakage current due to tunnel current will suddenly increase, so that power consumption will suddenly increase.
Further, in a case of an N-channel type transistor whose gate has been formed using n-type polycrystalline silicon having high impurity concentration, when a positive potential is applied to the gate, its portion in the vicinity of the gate insulator (ranging from 0.2 nm to 0.5 nm in thickness) becomes depleted, which results in that the effective thickness of the gate insulator becomes large. This becomes a serious problem when the thickness of the gate insulator is 2 nm or less.
Palliative solutions have been suggested with respect to these problems but no essential solutions have been found yet. For example, as for the thickness of the gate insulator, a material having a higher dielectric constant than silicon oxide (high-k material) is used for the gate insulator. As for the short-channel effect, the high-k material can provide substantially the same effect as the thin gate insulator of silicon oxide even when the physical thickness of the gate insulator is increased.
However, as a result of comparison of the energy difference between the bottom of the conduction band of silicon and the bottom of the conduction band of an insulator, that of hafnium oxide is approximately 1.5 eV and there are no other materials that surpass silicon oxide (3.5 eV); therefore high-k materials are generally disadvantageous in terms of electrical insulation (see Non-Patent Document 2).
Further, as shown in FIG. 2A, a method has been suggested in which the impurity concentration of the channel region is maintained to be low by forming regions with relatively high impurity concentration (halo regions 205a and 205b) in the vicinity of a source 202a and a drain 202b (see Patent Document 1). However, it cannot be said that this is an effective means for a short channel length of 100 nm or less.
For example, in the case where the channel length is 50 nm or less, it is necessary to suppress the outflow of carriers from extension regions 203a and 203b in the vicinity of the channel region. Along with the shortening of the channel, the impurity concentration of the extension regions 203a and 203b increases. In order to suppress the carrier injection from the extension regions 203a and 203b, it becomes necessary to also increase the concentration of the halo regions 205a and 205b. Specifically, in the case where the channel length is 50 nm or less, the impurity concentration of each of the halo regions 205a and 205b is required to be 5×1018 cm−3 or more.
Needless to say, in the structure shown in FIG. 2A, the carriers flowing between the source and the drain move from the extension region 203a to the extension region 203b through the halo regions 205a and 205b having high impurity concentration. When the regions with high impurity concentration exist in the route, impurity scattering is large; therefore, the mobility decreases.
In addition, the existence of the regions with high impurity concentration in the route increases the aforementioned variation in threshold value. Further, ion implantation at an oblique angle to the gate is necessary for forming the halo regions 205a and 205b outside the extension regions 203a and 203b. It is reported that, in this process, the gate insulator near the gate edge is damaged due to high-speed ions and the trap levels increase.
Boron is often used as a p-type impurity for forming the halo regions or the like. Actually, it is not an exaggeration to say that there are no practical p-type impurities other than boron. However, boron is easy to diffuse due to its small ionic radius and boron ions are very widely distributed at the time of ion implantation due to its small atomic weight. Specifically, boron exhibits a transient enhanced diffusion characteristic, and it is known that boron diffuses abnormally during thermal activation.
Considering the properties of boron as above, it is extremely difficult to provide the impurity region with steep concentration distribution by using boron. Therefore, in fact, boron is implanted even to the channel region at a concentration of 5×1018 cm−3 or more besides the halo regions 205a and 205b. 
As a method for decreasing the impurity concentration without the use of the halo region and suppressing the short-channel effect, as shown in FIG. 2B, a fully depleted transistor having a silicon-on-insulator (SOI) structure has been suggested in which a buried insulator 307 is formed extremely thinly, a channel region 308 having extremely low impurity concentration is provided in an SOI layer 306 provided over the buried insulator 307, and the channel region 308 is depleted by applying bias from a semiconductor substrate 301 below the buried insulator 307 (see Patent Document 2).
In order to deplete the channel region with bias from the substrate 301 in this manner, the thickness of each of the SOI layer 306 and the buried insulator 307 needs to be 20 nm or less; however, it is technically very difficult to form the SOI layer 306 and the buried insulator 307 with such a small thickness. From the perspective of mass productivity, the thickness of each of the SOI layer 306 and the buried insulator 307 is preferably 50 nm or more; however, the transistor shown in FIG. 2B does not sufficiently operate under such a condition.
On the other hand, as for the depletion of the gate, as shown in FIG. 2C, a method in which p-type silicon is used for a gate 404 in an accumulation type transistor with an SOI structure or a method in which a p-type silicon layer or a p-type silicon substrate 401 is provided for a side opposite to the gate 404 via a buried insulator 407 with a thickness of 20 nm or less has been suggested (see Patent Document 3).
However, boron is used as the p-type impurity also in this case. Therefore, as aforementioned, when boron-added silicon is used for the gate 404, particularly in the case where the physical thickness of the gate insulator is 2 nm or less, boron diffuses even to the channel region 408 through the gate insulator, which causes the variation in threshold value of the transistor. Moreover, when boron is implanted to the SOI substrate through the channel region by an ion implantation method, as a matter of course, a large amount of boron is implanted to the channel region 408, which also causes the variation in threshold value.
Also in this case, the thickness of the SOI layer 406 needs to be much smaller than the channel length, and specifically needs to be 20 nm or less, which is an obstacle in terms of mass productivity.